Chip package and method for manufacturing the same

ABSTRACT

In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.

This application is a divisional of Ser. No. 09/250,282, filed Feb. 16,1999, now U.S. Pat. No. 6,249,053, issued Jun. 19, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a chip package and a method formanufacturing the same more particularly, to a chip package of the typethat has an interconnection pattern and ball pads formed by etching ametal layer on one side or both sides of a resin substrate, whichincludes a package, such as a BGA package, or a flip chip package and ismainly used as a package, for mounting a chip such as a LSI chip, and amethod for manufacturing the same.

2. Description of the Relevant Art

Recently, a BGA (Ball Grid Array), a flip chip package and the like,which can be made to have more terminals have attracted attention sincea semiconductor apparatus is requested to have a higher density and ahigher speed. The BGA is most suitable for packaging of ICs, such as amicroprocessor and an ASIC, which are required to have more terminals,and has the following characteristics.

(a) Since balls are arranged in a plane, it is possible to have moreterminals than packaging technologies using a lead frame, such as a QFP(Quad Flat Package), and it is also possible to have still moreterminals than a PGA (Pin Grid Array).

(b) Since a BGA has a larger lead pitch than the QFP, the precision of amounter or the like is not always required to be high, and so thepackaging yield is improved.

(c) The cost is relatively low.

(d) The heat dissipation property is excellent, so that the impedancecan be low.

Untill recently, attention had been paid to a ceramic BGA among BGAsfrom the viewpoint of reliability, but the priority is moving to plasticarray packages from the viewpoint of cost reduction. In the plasticarray packages of this kind, there are PBGA (Plastic BGA), TBGA (TapeBGA), μ-BGA, CSP (Chip Size Package, Chip Scale Package) and the like ina broader sense.

An example of the PBGA is shown in FIG. 1. On the IC chip 11 mountingsurface of a resin substrate 12, an interconnection pattern 13 isformed, while on the other surface thereof, a large number of ball pads14 are formed. These ball pads 14 and the interconnection pattern 13 areconnected through through holes 16 for interconnection. The bottomsurface of the IC chip 11 is connected to the ball pads 14 throughthrough holes 17 for heat dissipation. On the ball pads 14, solder balls15 are deposited. The interconnection pattern 13 is connected to padsformed on the IC chip 11 (not shown) through bonding pads 13 a and wirebonders 18. The portion which includes the IC chip 11, the wire bonders18, and the majority of the interconnection pattern 13 is covered with amold resin 19.

Ordinarily, the bonding pads 13 a and the ball pads 14 are Ni/Au plated(not shown) in order to improve the bonding property and the depositionproperty of the solder balls 15, and for that purpose theinterconnection for electroplating is formed as shown in FIG. 2, forexample. Each of the bonding pads 13 a and ball pads 14 is connected toa tie bar 21 through a lead for plating 20. After the plating isfinished, each device is made by cutting on cutting lines 22. Theportion which need not be plated is previously covered with a soldermask 23 before the plating treatment.

An example of a BGA with a heat spreader is shown in FIGS. 3 and 4. BT(Bismaleimide Triazine) is used for forming a tape-shaped thin resinsubstrate 32. Since the BT resin has almost the same thermaltransformation temperature (300° C.) as a polyimide resin and has betteradhesiveness to a copper foil and workability than the polyimide resin,it is used widely for LSI packages. On the bottom surface of the resinsubstrate 32, an interconnection pattern (not shown) and ball pads 34are formed by etching a copper foil. On the ball pads 34, solder balls15 are deposited. Onto the top surface of the resin substrate 32, a Curing 33 having a cavity 35 to accomodate an IC chip 11 is adhered. Ontothe top surface of the Cu ring 33, a Cu heat spreader 38 is furtheradhered through an adhesive sheet 38 a. In the center portion of theresin substrate 32, a dam 36 is formed so as to surround the cavity 35.After connecting wire bonders 18, an injection mold resin 39 is injectedinto the cavity 35 to be solidified. The ball pads 34 and bonding pads(not shown) comprise a Cu layer 34 a and a Ni/Au layer 34 b as shown inFIG. 4. A solder mask 43 is formed around the Ni/Au layer 34 b.

In the BGA with a heat spreader of the type shown in FIG. 3, since it isdifficult to arrange the leads for plating 20 shown in FIG. 2 from theviewpoint of space, the Ni/Au layer 34 b is formed by electrolessplating. The leads for plating 20 and tie bars 21 shown in FIG. 2 arenot formed during the manufacturing process.

An example of a conventional flip chip package wherein a semiconductorcomponent is mounted by flip chip bonding is shown in FIGS. 5 and 6. Onthe chip 11 mounting surface of a resin substrate 12, an interconnectionpattern 13 and ball pads 14 a are formed, while on the other surfacethereof, a large number of ball pads 14 b are formed. These ball pads 14b and the interconnection pattern 13 are connected through through holes16 for interconnection. The ball pads 14 a under the chip 11 areconnected to the ball pads 14 b through through holes 17 for heatdissipation. On the ball pads 14 b, solder balls 15 are deposited. Theinterconnection pattern 13 is connected to the chip 11 through thesolder balls 15 deposited on the ball pads 14 a. The space between thechip 11 and the resin substrate 12 is charged with a mold resin 19. Onthe portion of the interconnection pattern 13 except the ball pads 14 aand 14 b, a solder mask 23 is formed. The ball pads 14 a and 14 bcomprise a Cu layer 34 a and a Ni/Au layer 34 b as shown in FIG. 6 andthe solder mask 23 is formed around the Ni/Au layer 34 b.

The Ni/Au layer 34 b in the flip chip package shown in FIGS. 5 and 6 isformed not by electroplating but by electroless plating. This is becauseflip chip packages tend to have high-density interconnections, and so itis difficult to form leads for electroplating between the high-densityinterconnections.

In the PBGA of the type shown in FIGS. 1 and 2, a large number of leadsfor plating 20 connected to each bonding pad 13 a or ball pad 14 and tiebars 21 must be formed for electroplating, which prevents theinterconnection pattern 13 and ball pads 14 from having a higherdensity. The leads for plating 20 inside the cutting lines 22 are lefteven after plating, leading to a possibility that they become a sourceof reflected noise, which adversely affects the electrical properties.

On the other hand, since the electroless plating is conducted in the BGAwith a heat spreader of the type shown in FIGS. 3 and 4, the leads forplating 20 and the tie bars 21 need not be formed, and so there is noproblem with density increasing of the interconnections and the like.However, the adhesive strength of the solder balls 15 to the ball pads34 is low, so that the adhesion tends to be unstable.

Since the electroless plating is conducted in the flip chip package ofthe type shown in FIGS. 5 and 6 in the same manner as in the BGA with aheat spreader of the type shown in FIGS. 3 and 4, the leads for plating20 and the tie bars 21 need not be formed and so there is no problemwith increasing density of the interconnections and the like. However,the adhesive strength of the solder balls 15 to the ball pads 14 a and14 b is low, so that the adhesion tends to be unstable.

SUMMARY OF THE INVENTION

The present invention was developed in order to solve the aboveproblems. It is an object of the present invention to provide a chippackage wherein leads for plating need not be formed so as to enable therealization of higher density and an improvement of electricalproperties while the plating is conducted by electroplating so that theadhesive strength of solder balls to pads is secured, and a method formanufacturing the same.

In order to achieve the above object, a chip package (1), according tothe present invention has an interconnection pattern and ball padsformed by etching a metal layer on one side or both sides of a resinsubstrate, and is characterized by the surface of the interconnectionpattern and ball pads which is coated with Ni and Au films byelectroplating, and no leads for electroplating are formed since anelectric current is applied to the metal layer during electroplating.

In the chip package (1), since an electric current is applied to themetal layer during electroplating, the leads for electroplating usuallyrequired are not needed. As a result, it is possible to inhibit theleads from preventing the density increasing and from deteriorating theelectrical properties. Since the plating for forming the Ni and Au filmsis conducted by electroplating, a sufficient value of adhesive strengthof the solder balls can be obtained.

A chip package (2) according to the present invention is characterizedby the metal layer which includes a copper foil and an electrolesscopper plating layer in the chip package (1).

In the chip package (2), an adequate thickness of the metal layer can besecured, the copper foil has an excellent adhesiveness to the resinsubstrate and strength, and a large current can passed through thecopper foil during the formation of the Ni and Au films byelectroplating.

A chip package (3) according to the present invention is characterizedby the metal layer which includes an electroless copper plating layer inthe chip package (1).

In the chip package (3), the metal layer comprising the electrolesscopper plating layer can be formed to be thin, i.e., micron or so. As aresult, the subsequent etching in patterning becomes easy and thequantity of overhang during etching is as small as possible, and so theinterconnection pattern can easily have a higher density.

A chip package (4) according to the present invention is characterizedby through holes formed in the resin substrate, having side walls whichare coated with Ni and Au films by electroplating in one of the chippackages (1)-(3).

Conventionally, only Cu plating is conducted on the side walls of thethrough holes, not Ni/Au plating. But in the chip package (4), since theNi/Au plating film is formed by electroplating, not only the surface ofthe interconnection pattern and ball pads but also the side walls of thethrough holes, the reliability of the chip package can be improved.

A method for manufacturing a chip package (1) according to the presentinvention includes the steps of:

forming a plating resist pattern on the surface of a metal layer formedon one side or both sides of a resin substrate;

applying an electric current to the metal layer to form Ni and Au filmsby electroplating on the metal layer surface which is not covered withthe plating resist pattern; and

removing the plating resist pattern to etch the metal layer using theNi/Au film as an etching mask.

In the method for manufacturing a chip package (1), since the Ni/Au filmis formed by electroplating on the portion of the metal layer surfacewhich is not covered with the plating resist pattern, then the metallayer used for the passage of electric current is etched using the Ni/Aufilm as an etching mask. Therefore the interconnection pattern and ballpads made of the metal layer/Ni/Au film can be formed without formingleads for electroplating only if the metal layer surface except aportion to be an interconnection pattern and ball pads is covered withthe plating resist pattern. Furthermore, since the Ni/Au film is formedby electroplating, it has sufficient adhesive strength to the solderballs.

A method for manufacturing a chip package (2) according to the presentinvention is characterized by the metal layer comprising a copper foil,an electroless copper plating layer, and an electrolytic copper platinglayer in the method for manufacturing a chip package (1).

In the method for manufacturing a chip package (2), the electrolesscopper plating layer and electrolytic copper plating layer can be formedin the through holes formed in the resin substrate before forming theNi/Au film by electroplating, and the Ni/Au film can be also formed inthe through holes by electroplating. As a result, the reliability of thechip package can be improved.

A method for manufacturing a chip package (3) according to the presentinvention is characterized by the metal layer comprising an electrolesscopper plating layer, or a copper foil and an electroless copper platinglayer in the method for manufacturing a chip package (1).

In the method for manufacturing a chip package (3), by forming theelectroless copper plating layer after forming the through holes in theresin substrate, the metal layer for the interconnection pattern andball pads and the metal layer for the through holes can be formed at thesame time, leading to the simplification of the chip packagemanufacturing process. The electroless copper plating layer can beformed to be thin, i.e., 1 micron or so. As a result, the subsequentetching of the electroless copper plating layer as a metal layer becomeseasy. The quantity of overhang during the etching of the electrolesscopper plating layer can be made as small as possible, therefore ahigh-density interconnection pattern can be easily achieved. When themetal layer comprises a copper foil and an electroless copper platinglayer, the adhesive strength of the metal layer to the resin substratecan be increased in addition to the above effects.

A method for manufacturing a chip package (4) according to the presentinvention is characterized by including the step of conductingelectroless plating and electroplating treatment of copper on the sidewalls of through holes after forming the through holes in the resinsubstrate, in one of the methods for manufacturing a chip package(1)-(3).

In the method for manufacturing a chip package (4), since a plating filmof Cu which is a good conductor is formed on the side walls of thethrough holes before the Ni/Au plating treatment by electroplating, theNi/Au plating film can be also formed on the side walls of the throughholes by electroplating. As a result, the reliability of the chippackage can be improved.

A method for manufacturing a chip package (5) according to the presentinvention is characterized by using a dry film resist having a principalconstituent of an acrylic resin for forming the plating resist patternin one of the methods for manufacturing a chip package (1)-(3).

The dry film resist having a principal constituent of an acrylic resinhas high resistance to the Cu/Ni/Au plating solution and is favorablystripped by a release solution so that no residue of stripping iscaused. Therefore, in the method for manufacturing a chip package (5), aprecise interconnection pattern and ball pads can be formed, thereforethe occurrence rate of shorting can be easily reduced.

A method for manufacturing a chip package (6) according to the presentinvention is characterized by using a liquid resist having a principalconstituent of an acrylic resin for forming the plating resist patternin one of the methods for manufacturing a chip package (1)-(3).

The liquid resist having a principal constituent of an acrylic resin hasexcellent adhesiveness to the metal layer so that the pattern formationis precisely conducted, and has high resistance to the Cu/Ni/Au platingsolution and is favorably stripped by a release solution so that noresidue of stripping is caused. Therefore, in the method formanufacturing a chip package (6), a fine interconnection pattern andball pads can be precisely formed, therefore the occurrence rate ofshorting can be easily reduced.

A method for manufacturing a chip package (7) according to the presentinvention is characterized by conducting cleaning treatment on the metallayer surface before forming the plating resist pattern in the methodfor manufacturing a chip package (5).

By conducting the cleaning treatment, the adhesiveness of the platingresist pattern to the metal layer surface is improved. As a result, theplating solution is prevented from penetrating under the plating resistpattern during electroplating so that the occurrence of shorting in theinterconnection pattern can be inhibited.

A method for manufacturing a chip package (8) according to the presentinvention is characterized by conducting bake treatment on a platingresist and/or plating resist pattern before forming Ni and Au films byelectroplating in one of the methods for manufacturing a chip package(1)-(3).

By the bake treatment, the optical setting reaction and/or thermosettingreaction of the plating resist is accelerated so that the adhesivestrength thereof to the base metal layer is higher.

A method for manufacturing a chip package (9) according to the presentinvention is characterized by using an alkaline solution having aprincipal constituent of copper ammine complex or tetraamminecopper (II)chloride as an etchant of the metal layer in the method formanufacturing a chip package (2).

The alkaline solution having a principal constituent of a copper aminecomplex or a tetraamminecopper (II) chloride can etch only the Cu layerefficiently, without dissolving the Ni and Au films. Therefore, themetal layer can be etched efficiently using the electroplating film ofNi/Au as an etching mask.

A method for manufacturing a chip package (10) according to the presentinvention is characterized by using a soft etching solution having aprincipal constituent of a soda persulfate or mixture of hydrogenperoxide and sulfuric acid as an etchant of the metal layer, in themethod for manufacturing a chip package (3).

The soft etching solution having a principal constituent of a sodapersulfate or mixture of hydrogen peroxide and sulfuric acid can etchthe Cu layer efficiently without dissolving the Au film. In addition,the soft etching solution is milder than the alkaline solution having aprincipal constituent of copper ammine complex or tetraamminecopper (II)chloride. Therefore, when the metal layer is an electroless copperplating layer, or a copper foil and an electroless copper plating layerwith the electroplating film of Ni/Au used as an etching mask, theelectroless copper plating layer, or the copper foil and electrolesscopper plating layer can be precisely efficiently with almost nooverhang thereon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing an example of a conventional PBGA;

FIG. 2(a) is a top view showing a conventional BT substrate on whichleads for plating are formed, and FIG. 2(b) is a sectional view thereof;

FIG. 3 is a sectional view showing an example of a conventionaltwo-layer BGA with a heat spreader;

FIG. 4 is an enlarged sectional view showing a ball pad and itsperiphery;

FIG. 5 is a sectional view showing an example of a conventional flipchip package;

FIG. 6 is an enlarged sectional view showing a ball pad and itsperiphery;

FIGS. 7(a)-(d) are sectional views showing part of the manufacturingprocess of a BGA package according to the embodiment (1) of the presentinvention;

FIGS. 8(a)-(d) are sectional views showing part of the manufacturingprocess of a BGA package according to the embodiment (1) of the presentinvention;

FIGS. 9(a)-(c) are sectional views showing part of the manufacturingprocess of a BGA package according to the embodiment (1) of the presentinvention;

FIGS. 10(a)-(c) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (2) of thepresent invention;

FIGS. 11(a)-(c) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (2) of thepresent invention:

FIGS. 12(a) and 12(b) are sectional views showing part of themanufacturing process of a flip chip package according to the embodiment(2) of the present invention;

FIG. 13 is a sectional view showing an example of a flip chip packageaccording to an embodiment;

FIGS. 14(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (3) of thepresent invention;

FIGS. 15(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (3) of thepresent invention;

FIGS. 16(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (3) of thepresent invention;

FIGS. 17(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (3) of thepresent invention;

FIGS. 18(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (4) of thepresent invention;

FIGS. 19(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (4) of thepresent invention;

FIGS. 20(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (4) of thepresent invention;

FIGS. 21(a)-(d) are sectional views showing part of the manufacturingprocess of a flip chip package according to the embodiment (4) of thepresent invention;

FIGS. 22(a) and 22(b) are enlarged sectional views showing a Ni/Au layerformed on an interconnection pattern according to an example;

FIG. 23 is an enlarged sectional view showing a Ni/Au layer formed on aball pad according to an example: and

FIG. 24 is an enlarged sectional view showing a Ni/Au layer formed on aball pad according to an example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the chip package and the method formanufacturing the same according to the present invention are describedbelow by reference to the Figures.

FIG. 7 is a diagrammatic sectional view showing part of themanufacturing process of a BGA package with a heat spreader according tothe embodiment (1). In FIG. 7, reference numeral 1 represents acopper-covered laminate. The copper-covered laminate 1 comprises a resinsubstrate 2 and copper foils 3 adhered onto both main surfaces thereof(FIG. 7(a)). Punching of through holes 4 and a cavity 5 is conducted onthe copper-covered laminate 1 (FIG. 7(b)). Panel plating treatment byelectroless and electrolytic copper platings is conducted on thecopper-covered laminate 1 in which the through holes 4 and the cavity 5are formed. The copper foils 3 adhered onto the top and bottom surfacesof the resin substrate 2 are electrically connected through the throughholes 4 (Cu layers 6 by electroless and electrolytic copper platings)(FIG. 7(c)). The copper-covered laminate 1 is adhered to a Cu plate 7through an adhesive sheet 7 a (FIG. 7(d)).

Cleaning treatment is conducted on the top surface of the copper foil 3(upper side in the figure). The cleaning treatment is conducted in orderto increase the adhesiveness of a DFR (Dry Film Resist) 8 which is to beadhered thereto later. In more concrete terms, jet scrubbing (mechanicalpolishing by buffing), acid cleaning with sulfuric acid, and jetscrubbing or the like are conducted. Onto the copper foil 3 on which thecleaning treatment is conducted, the DFR (Dry Film Resist) 8 having aprincipal constituent of acrylic resin is adhered. Exposure treatmentwherein the inverse pattern of the interconnection pattern is developedis conducted on the DFR 8, and PEB (Post Exposure Bake) treatment isconducted before developing in order to improve the adhesive strength byaccelerating the optical setting reaction through the exposure. The DFR8 is developed so that the DFR 8 of the inverse pattern is left, andpost bake treatment is conducted in order to improve the adhesivestrength by accelerating the thermosetting reaction (FIG. 8(a)).

In order to form a Ni/Au layer 9 on the surface of the copper foil 3 andpanel plating layer by electroless and electrolytic copper platingswhich is not covered with the DFR 8, the laminated body of thecopper-covered laminate 1 and the Cu plate 7 is dipped into a platingsolution and applying an electric current thereto, electroplating isconducted (FIG. 8(b). After rinsing the plating solution sufficiently,the laminated body is dipped into an about 3% NaOH aqueous solution of50° C. in order to strip and remove the DFR 8. After removing the DFR 8(FIG. 8(c)), etching is conducted on the copper foil 3 and panel platinglayer by electroless and electrolytic copper platings using the formedNi/Au layer 9 as a mask. As an etching solution, a solution which etchesonly the copper foil 3 and panel plating layer by electroless andelectrolytic copper platings without etching the Ni/Au layer 9 isneeded. An alkaline solution having a principal constituent of copperammine complex or tetramminecopper (II) chloride and the like can beused. By the etching treatment, an interconnection pattern 10 includinga pad portion wherein the electroplating film of the Ni/Au layer 9 isformed on the Cu interconnection is formed (FIG. 8(d)).

A solder mask 43 is formed on a portion of the interconnection pattern10 except the bonding pads and ball pads 34 (FIG. 2) (FIG. 9(a)). A heatspreader 38 is further laminated on the laminated body of thecopper-covered laminate 1 and the Cu plate 7 through an adhesive sheet 7b (FIGS. 9(b) and 9(c)).

According to the embodiment (1), the copper foil 3 and panel platinglayer by electroless and electrolytic copper platings themselvesfunction as conventional leads for plating 20 (FIG. 2), so that theNi/Au layer 9 can be formed by electroplating on the interconnectionpattern 10 without forming the leads for plating 20. As a result, itbecomes easy to make the interconnection pattern 10 have a higherdensity, and there is no reflection caused by the partially remainingleads for plating 20, so that the electrical properties can be improved.Furthermore, since the Ni/Au layer 9 is formed by electroplating, asufficiently large value of adhesive strength of wire bonding and solderballs 15 (FIG. 3) can be obtained. Since the Ni/Au layer 9 is alsoformed by electroplating on the side walls of the through holes 4, thereliability of the electrical connection through the through holes 4 canbe improved.

The DFR 8 having a principal constituent of acrylic resin has highresistance to the plating solution used in the formation of the Ni/Aulayer 9. It is favorably stripped by a release soultion such as a NaOHaqueous solution so that a residue of stripping is not caused.Therefore, it is easy to form the interconnection pattern 10 precisely,and so shorting between interconnections is not easily caused. Since theadhesiveness of the DFR 8 to the panel plating layer by electroless andelectrolytic copper platings can be made higher by the cleaning and baketreatment, the penetration of the plating solution under the DFR 8 canbe more certainly prevented.

Since the alkaline solution having a principal constituent of copperammine complex or tetraamminecopper (II) chloride is used as an etchantof the copper foil 3 and panel plating layer by electroless andelectrolytic copper platings, only the copper foil 3 and panel platinglayer by electroless and electrolytic copper platings can be etchedefficiently without dissolving the Ni/Au layer 9.

In the above embodiment (1), a two-layer construction wherein the copperfoils 3 are adhered to both main surfaces of the resin substrate 2 isdescribed as an example, but in another embodiment, a four-layerconstruction wherein two copper-covered laminates 1 are laminated isalso available. Furthermore, a BGA construction having a usual PBGAconstruction without a heat spreader is also available as a matter ofcourse.

FIGS. 10-12 are diagrammatic sectional views showing part of themanufacturing process of a flip chip package according to the embodiment(2), and in the figure, reference numeral 1 represents a copper-coveredlaminate. The copper-covered laminate 1 comprises a resin substrate 2and copper foils 3 adhered onto both main surfaces thereof (FIG. 10(a)).Punching of through holes 4 is conducted on the copper-covered laminate1 (FIG. 10(b)). Panel plating treatment by electroless and electrolyticcopper platings is conducted on the copper-covered laminate 1 in whichthe through holes 4 are formed, and the copper foils 3 adhered onto thetop and bottom surfaces of the resin substrate 2 are electricallyconnected through the through holes 4 (Cu layers 6 by electroless andelectrolytic copper platings) (FIG. 10(c)).

Cleaning treatment is conducted on the surfaces of the Cu layers 6 ofpanel plating by electroless and electrolytic copper platings. Thecleaning treatment is conducted in order to increase the adhesiveness ofa DFR 8 which is to be adhered thereto later, and in more concreteterms, jet scrubbing (mechanical polishing by buffing), acid cleaningwith sulfuric acid, and jet scrubbing or the like are conducted. Ontothe Cu layers 6 of panel plating by electroless and electrolytic copperplatings on which the cleaning treatment is conducted, the DFRs 8 havinga principal constituent of acrylic resin are adhered. Exposure treatmentwherein the inverse pattern of the interconnection pattern is developedis conducted on the DFRs 8, and PEB (Post Exposure Bake) treatment isconducted before developing in order to improve the adhesive strength byaccelerating the optical setting reaction through the exposure. The DFRs8 are developed so that the DFRs 8 of the inverse pattern are left, andpost bake treatment is conducted in order to improve the adhesivestrength by accelerating the thermosetting reaction (FIG. 11(a)).

In order to form Ni/Au layers 9 on the surfaces of the Cu layers 6 ofpanel plating by electroless and electrolytic copper platings which arenot covered with the DFRs 8, the copper-covered laminate 1 is dippedinto a plating solution, an electric current is applied thereto, andelectroplating is conducted (FIG. 11(b)). After rinsing the platingsolution sufficiently, the laminate is dipped into an about 3% NaOHsolution of 50° C. in order to strip and remove the DFRs 8. Afterremoving the DFRs 8 (FIG. 11(c)), etching is conducted on the copperfoils 3 and Cu layers 6 of panel plating by electroless and electrolyticcopper platings using the formed Ni/Au layers 9 as a mask. As an etchingsolution, a solution which etches only the copper foil 3 and Cu layer 6of panel plating by electroless and electrolytic copper platings withoutetching the Ni/Au layer 9 is needed, and an alkaline solution having aprincipal constituent of copper ammine complex or tetraamminecopper (II)chloride or the like can be exemplified. By the etching treatment, aninterconnection pattern 10 including a pad portion wherein theelectroplating film of the Ni/Au layer 9 is formed on the Cuinterconnections is formed (FIG. 12(a)).

A solder mask 43 is formed on the portion of the interconnection pattern10 except ball pads 10 a for semiconductor component connection and ballpads 10 b for mother board connection (FIG. 12(b)).

An example of a flip chip package manufactured by the method describedin FIGS. 10-12 is shown in FIG. 13. On the flip chip 11 mounting surfaceof the resin substrate 2, the interconnection pattern 10 including theball pads 10 a to which terminals of the flip chip 11 are connected isformed, while on the other surface, the ball pads 10 b to which solderballs 15 for mother board connection are connected are formed. Theinterconnection pattern 10 (ball pads 10 a ) and the ball pads 10 b areconnected through the through holes 4 for interconnection, and on theball pads 10 b, the solder balls 15 are deposited. The interconnectionpattern 10 is connected to the terminals of the flip chip 11 throughsolder balls 18 a deposited on the ball pads 10 a. A resin layer 19 a isformed between the flip chip 11 and the resin substrate 2.

According to the embodiment (2), the copper foil 3 and Cu layer 6 ofpanel plating by electroless and electrolytic copper platings themselvesfunction as conventional leads for electroplating 20(FIG. 2), so thatthe Ni/Au layer 9 can be formed by electroplating on the interconnectionpattern 10 including the ball pads 10 a and 10 b without forming theleads for plating 20. Therefore, even when the electroplating techniqueis adopted, it is possible to make the interconnection pattern 10 have ahigher density in the same manner as when the electroless platingtechnique is adopted. No reflection is caused by the partially remainingleads for plating 20, so that the electrical properties are notdeteriorated. Furthermore, since the Ni/Au layer 9 is formed byelectroplating, a sufficiently large value of adhesive strength of thesolder balls 15 and 18 a to the ball pads 10 a and 10 b can be obtained.

Since the Ni/Au layer 9 is also formed by electroplating on the sidewalls of the through holes 4, the reliability of the electricalconnection through the through holes 4 is be improved.

The DFR 8 having a principal constituent of acrylic resin has highresistance to the Ni/Au plating solution, and is favorably stripped by arelease solution such as a NaOH solution so that a residue of strippingis not caused. Therefore, it is easy to form the interconnection pattern10 precisely, and so shorting between interconnections is not easilycaused. Since the adhesiveness of the DFR 8 to the copper foil 3 can bemade higher by the cleaning and bake treatment, the penetration of theplating solution under the DFR 8 can be certainly prevented.

Since the alkaline solution having a principal constituent of copperamine complex or tetraamminecopper (II) chloride is used as an etchantof the copper foil 3, only the copper foil 3 and Cu layer 6 of panelplating by electroless and electrolytic copper platings can be etchedefficiently without dissolving the Ni/Au layer 9.

FIGS. 14-17 are diagrammatic sectional views showing part of themanufacturing process of a flip chip package according to the embodiment(3), and in the figures, reference numeral 1 represents a copper-coveredlaminate. The copper-covered laminate 1 comprises a resin substrate 2and copper foils 3 adhered onto both main surfaces thereof (only onesurface shown) (FIGS. 14(a) and 16(a)). Punching of through holes 4 isconducted on the copper-covered laminate 1 (FIG. 16(a)). In order tostrip and remove the copper foils 3, etching treatment using a FeCl₃solution is conducted. Then to make the deposition of electroless copperbetter in the subsequent electroless copper plating treatment, roughingtreatment using a permanganic acid solution for surface roughing isconducted on the surfaces of the resin substrate 2 from which the copperfoils 3 are removed (FIGS. 14(b) and 16(b)).

Panel plating treatment by electroless copper plating is conducted overall of both main surfaces of the resin substrate 2 including the sidewalls of the through holes 4 so that electroless copper plating layers 6a having a thickness of one tenth or so of the thickness of the copperfoil 3 are formed. The electroless copper plating layers 6 a formed onthe top and bottom surfaces of the resin substrate 2 are electricallyconnected through the through holes 4 (FIGS. 14(c) and 16(c)).

Cleaning treatment is conducted on the surfaces of the electrolesscopper plating layers 6 a. The cleaning treatment is conducted in orderto increase the adhesiveness of a DFR 8 which is to be adhered theretolater, and in more concrete terms, jet scrubbing (mechanical polishingby buffing), acid cleaning with sulfuric acid, and jet scrubbing or thelike are conducted. Onto the electroless copper plating layers 6 a onwhich the cleaning treatment is conducted, the DFRs (Dry Film Resists) 8having a principal constituent of acrylic resin are adhered. Exposuretreatment wherein the inverse pattern of the interconnection pattern isdeveloped is conducted on the DFRs 8, and PEB (Post Exposure Bake)treatment is conducted before developing in order to improve theadhesive strength by accelerating the optical setting reaction throughthe exposure. The DFRs 8 are developed so that the DFRs 8 of the inversepattern are left, and post bake treatment is conducted in order toimprove the adhesive strength by accelerating the thermosetting reaction(FIGS. 14(d) and 16(d)).

In order to form electrolytic copper plating layers 6 b on the surfacesof the electroless copper plating layers 6 a which are not covered withthe DFRs 8, the resin is dipped into a plating solution, an electriccurrent is applied thereto, and electroplating is conducted (FIGS. 15(a)and 17(a)). Then in order to form Ni/Au layers 9 by electroplating onthe surfaces of the electrolytic copper plating layers 6 b which are notcovered with the DFRs 8, the resin substrate 2 is dipped into a platingsolution, an electric current is applied thereto, and electroplating isconducted (FIGS. 15(b) and 17(b)). After rinsing the plating solutionsufficiently, the substrate is dipped into an about 3% NaOH aqueoussolution of 50° C. in order to strip and remove the DFRs 8. Afterremoving the DFRs 8 (FIGS. 15(c) and 17(c)), etching is conducted on theelectroless copper plating layers 6 a using the formed Ni/Au layers 9 asa mask. As an etching solution, a solution which etches only theelectroless copper plating layer 6 a without etching the Ni/Au layer 9is preferable. But since the electroless copper plating layer 6 a can bemade thinner by an order of magnitude or so than the copper foil 3, itcan be etched even without using the alkaline solution having aprincipal constituent of copper ammine complex or tetraamminecopper (II)chloride used in the above embodiments (1) and (2). For example, a softetching solution of such as sodium persulfate or mixture of hydrogenperoxide and sulfuric acid can be used as an etching solution. By theetching treatment, an interconnection pattern 30 including a pad portionwherein the electroplating film of the Ni/Au layer 9 is formed on the Cuinterconnections made of the electroless copper plating layer 6 a andthe electrolytic copper plating layer 6 b is formed (FIGS. 15(d) and17(d)).

In the method for manufacturing a flip chip package according to theembodiment (3), the electroless copper plating layer 6 a itselffunctions as conventional leads for plating 20, so that the Ni/Au layer9 can be formed by electroplating on the interconnection pattern 30without forming the leads for plating 20. Furthermore, since theelectroless copper plating layer 6 a can be made thinner by an order ofmagnitude or so than the copper foil 3, the etching treatment of theelectroless copper plating layer 6 a for pattern formation becomesextremely easy, and the quantity of overhang can be made almost zero(one tenth or so of the case wherein the copper foil 3 is used). As aresult, it becomes further easier to make the interconnection pattern 30have a higher density, compared with the embodiment (1) or (2). Noreflection is caused by the partially remaining leads for plating 20, sothat the electrical properties can be improved. Furthermore, since theNi/Au layer 9 is formed by electroplating, a sufficiently large value ofadhesive strength of wire bonding and solder balls 15 (FIG. 13) can besecured.

Since the Ni/Au layer 9 is also formed by electroplating on the sidewalls of the through holes 4, the reliability can be improved.

The DFR 8 having a principal constituent of acrylic resin has highresistance to the plating solutions used in the formation of theelectrolytic copper plating layer 6 b and Ni/Au layer 9, and isfavorably stripped by a release solution such as a NaOH aqueous solutionso that no residue of stripping is caused. Therefore, it is easy to formthe interconnection pattern 30 precisely, and so shorting betweeninterconnections is not easily caused. Since the adhesiveness of the DFR8 to the electroless copper plating layer 6 a can be made higher by thecleaning and bake treatment, the penetration of the plating solutionunder the DFR 8 can be certainly prevented.

Since the soft etching solution having a principal constituent of sodapersulfate or mixture of hydrogen peroxide and sulfuric acid is used asan etchant of the electroless copper plating layer 6 a, the electrolesscopper plating layer 6 a can be etched efficiently without dissolvingthe Au layer and with only a small quantity of overhang of theelectroless copper plating layer 6 a. Moreover, the soft etchingsolution is easy to handle and the disposal of liquid waste is alsoeasy.

FIGS. 18-21 are diagrammatic sectional views showing part of themanufacturing process of a flip chip package according to the embodiment(4), and in the figure, reference numeral 2 represents a resinsubstrate. Copper foils 3 a which are considerably thinner (thickness of1-3 μm or so) than the above copper foils 3 (thickness of ten-odd μm orso) are bonded by thermocompression onto both main surfaces of the resinsubstrate 2 in a prepreg state (only one surface shown) (FIGS. 18(a) and20(a)). Punching of through holes 4 is conducted on the copper-coveredlaminate 1 a (FIG. 20(b)). Then in order to make the deposition ofelectroless copper better in the subsequent electroless copper platingtreatment, roughing treatment using a permanganic acid solution forsurface roughing is conducted on the surfaces of the copper-coveredlaminate 1 a (FIGS. 18(b) and 20(b)).

Panel plating treatment by electroless copper plating is conducted overall of both main surfaces of the copper-covered laminate 1 a includingthe side walls of the through holes 4 so that electroless copper platinglayers 6 a having a thickness of one third or so of the thickness of thecopper foil 3 a are formed. The electroless copper plating layers 6 aformed on the top and bottom surfaces of the copper-covered laminate laare electrically connected through the through holes 4 (FIGS. 18(c) and20(c)).

Cleaning treatment is conducted on the surfaces of the electrolesscopper plating layers 6 a. The cleaning treatment is conducted in orderto increase the adhesiveness of a DFR 8, which is to be adhered theretolater, and in more concrete terms, jet scrubbing (mechanical polishingby buffing), acid cleaning with sulfuric acid, and jet scrubbing or thelike are used. Onto the electroless copper plating layers 6 a on whichthe cleaning treatment is conducted, the DFRs (Dry Film Resists) 8having a principal constituent of acrylic resin are adhered. Exposuretreatment wherein the inverse pattern of the interconnection pattern isdeveloped is conducted on the DFRs 8, and PEB (Post Exposure Bake)treatment is conducted before developing in order to improve theadhesive strength by accelerating the optical setting reaction throughthe exposure. The DFRs 8 are developed so that the DFRs 8 of the inversepattern are left, and post bake treatment is conducted in order toimprove the adhesive strength by accelerating the thermosetting reaction(FIGS. 18(d) and 20(d)).

In order to form electrolytic copper plating layers 6 b on the surfacesof the electroless copper plating layers 6 a which are not covered withthe DFRs 8, the resin substrate is dipped into a plating solution, anelectric current is applied thereto, and electroplating is conducted(FIGS. 19(a) and 2l(a)). Then in order to form Ni/Au layers 9 byelectroplating on the surfaces of the electrolytic copper plating layers6 b which are not covered with the DFRs 8, the resin substrate 2 isdipped into a plating solution, an electric current is applied thereto,and electroplating is conducted (FIGS. 19(b) and 21(b)). After rinsingthe plating solution sufficiently, the substrate is dipped into an about3% NaOH aqueous solution of 50° C. in order to strip and remove the DFRs8. After removing the DFRs 8 (FIGS. 19(c) and 21(c)), etching isconducted on the electroless copper plating layers 6 a and copper foils3 a using the formed Ni/Au layers 9 as a mask. As an etching solution, asolution which etches the electroless copper plating layer 6 a andcopper foil 3 a without etching the Au layer is preferable. But sincethe electroless copper plating layer 6 a and copper foil 3 a can be madethinner by an order of magnitude or so than the copper foil 3, it can beetched even without using the alkaline solution having a principalconstituent of copper ammine complex or tetraamminecopper (II) chlorideused in the above embodiments (1) and (2). For example, a soft etchingsolution of such as soda persulfate or mixture of hydrogen peroxide andsulfuric acid can be used as an etching solution. By the etchingtreatment, an interconnection pattern 30 a including a pad portionwherein the electroplating film of the Ni/Au layer 9 is formed on the Cuinterconnections made of the copper foil 3 a, electroless copper platinglayer 6 a, and electrolytic copper plating layer 6 b is formed (FIGS.19(d) and 21(d)).

In the method for manufacturing a flip chip package according to theembodiment (4), the copper foil 3 a and electroless copper plating layer6 a themselves function as conventional leads for plating 20, so thatthe Ni/Au layer 9 can be formed by electroplating on the interconnectionpattern 30 a without forming the leads for plating 20. Furthermore,since the copper foil 3 a and electroless copper plating layer 6 a areconsiderably thinner than the copper foil 3, the etching treatment ofthe copper foil 3 a and electroless copper plating layer 6 a for patternformation becomes extremely easy, and the quantity of overhang can bemade smaller (one fifth or so of the case wherein the copper foil 3 isused). As a result, it becomes easier to make the interconnectionpattern 30 a have a higher density, compared with the embodiment (1) or(2). No reflection is caused by the partially remaining leads forplating 20, so that the electrical properties can be improved.Furthermore, since the Ni/Au layer 9 is formed by electroplating, asufficiently large value of adhesive strength of wire bonding and solderballs 15 (FIG. 13) can be secured. Since the Ni/Au layer 9 is alsoformed by electroplating on the side walls of the through holes 4, thereliability can be improved.

The DFR 8 having a principal constituent of acrylic resin has highresistance to the plating solutions used in the formation of theelectrolytic copper plating layer 6 b and Ni/Au layer 9, and isfavorably stripped by a release solution such as a NaOH aqueous solutionso that no residue of stripping is caused. Therefore, it is easy to formthe interconnection pattern 30 a precisely, and so shorting betweeninterconnections is not easily caused. Since the adhesiveness of the DFR8 to the electroless copper plating layer 6 a can be made higher by thecleaning and bake treatment, the penetration of the plating solutionunder the DFR 8 can be certainly prevented.

Since the soft etching solution having a principal constituent of sodapersulfate or mixture of hydrogen peroxide and sulfuric acid is used asan etchant of the copper foil 3 a and electroless copper plating layer 6a, the copper foil 3 a and electroless copper plating layer 6 a can beetched efficiently without dissolving the Au layer and with only a smallquantity of overhang of the copper foil 3 a and electroless copperplating layer 6 a. Moreover, the soft etching solution is easy to handleand the disposal of liquid waste is also easy. In the above embodiments(3) and (4), examples of the method for manufacturing a flip chippackage is described, but the manufacturing method according to thepresent invention is not limited to the method for manufacturing a flipchip package. Since the Ni/Au layer 9 is formed by electroplating in themanufacturing method according to the present invention, the thicknessof the Ni/Au layer 9 can be easily controlled unlike the case ofelectroless plating. By making the Ni/Au layer 9 thicker, themanufacturing method can be also applied to a method for manufacturing aBGA package of a wire bonding type in the same manner. In the aboveembodiment (3) the resin substrate 2 which is made by stripping andremoving the copper foils 3 from the copper-covered laminate 1 is used,but in another embodiment, the copper-covered laminate 1 is notnecessarily used, and the punching of the through holes 4 and the likecan be conducted on a resin substrate 2 as a starting material. In theabove embodiments (1)-(4), the DFR 8 is used as a plating mask, but theplating mask is not limited to the DFR 8. In another embodiment, aresist pattern can be formed using a liquid resist.

EXAMPLES

Examples of the chip package and the method for manufacturing the chippackage according to the present invention are described below.

Example 1

A BGA with a heat spreader was manufactured by the method shown in FIGS.7-9. The concrete manufacturing conditions were as follows.

Size of BT substrate: 500 mm×500 mm×thickness 0.1 mm

Thickness of copper foil 3: 12 μm

Diameter of through hole 4: 200 μm

Width of interconnection pattern 10: 90 μm

Diameter of ball pad: 400 μm

Chief material of DFR 8: acrylic resin

Constituents of Ni/Au plating solution: Nickel sulfate bath and goldcyanide bath

Cleaning treatment on copper foil 3: buffing, jet scrubbing, and acidcleaning

Bake treatment of DFR 8: 100° C., 30 min

Release solution of DFR 8: 3% NaOH solution, 50° C.

Etchant of Cu: alkaline solution of pH 8.0-8.5 of copper ammine complex

On the ball pads, bonding pads, and through holes 4, the Ni/Au films 9shown in FIG. 18 were formed.

Peel test of Ni/Au layer 9: by a peel test using a cellophane adhesivetape on the market, a preferable result, no peeling of the Ni/Au layer,could be obtained.

Example 2

A flip chip package shown in FIG. 13 was manufactured by the methodshown in FIGS. 10-12. The concrete manufacturing conditions were asfollows.

Material of resin substrate 2: BT (Bismaleimide Triazine)

Size of resin substrate 2: 500 mm×500 mm×thickness 100 μm

Thickness of copper foil 3: 12 μm

Diameter of through hole 4: 200 μm

Width of interconnection pattern 10: 90 μm

Diameter of ball pad 10 a: 100 μm

Diameter of ball pad 10 b: 400 μm

Chief material of DFR 8: acrylic resin

Constituents of Ni/Au plating solution: Nickel sulfate bath and goldcyanide bath

Cleaning treatment on copper foil 3: buffing, jet scrubbing, and acidcleaning

Bake treatment of DFR 8: 100° C. 30 min

Release solution of DFR 8: 3% NaOH solution, 50° C.

Etchant of Cu: alkaline solution of pH 8.0-8.5 of copper ammine complex

On the ball pads 10 a and 10 b and throughholes 4, the Ni/Au films 9shown in FIG. 19 were formed.

Example 3

A flip chip package was manufactured by the method shown in FIGS. 14-16.The concrete manufacturing conditions were as follows.

Material of resin substrate 2: BT (Bismaleimide Triazine)

Size of resin substrate 2: 500 mm×500 mm×thickness 100 μm

Thickness of electroless copper plating layer 6 a:1 μm

Diameter of through hole 4: 100 μm

Width of interconnection pattern 10: 40 μm

Diameter of ball pad 10 a: 50 μm

Diameter of ball pad 10 b: 100 μm

Chief material of DFR 8: acrylic resin

Constituents of Ni/Au plating solution: Nickel sulfate bath and goldcyanide bath

Cleaning treatment on electroless: buffing, jet scrubbing, and acidcopper plating layer 6 a cleaning

Bake treatment of DFR 8: 100° C., 30 min

Release solution of DFR 8: 3% NaOH solution, 50° C.

Etchant of Cu: soft etching solution of pH 7.0 of soda persulfate

On the ball pads and through holes 4, the Ni/Au films 9 shown in FIG. 24were formed.

Peel test of Ni/Au layer 9: by a peel test using a cellophane adhesivetape on the market, a preferable result, no peeling of the Ni/Au layer,could be obtained.

Example 4

A flip chip package was manufactured by the method shown in FIGS. 18-21.The concrete manufacturing conditions were as follows.

Material of resin substrate 2: BT (Bismaleimide Triazine)

Size of resin substrate 2: 500 mm×500 mm×thickness 100 μm

Thickness of copper foil 3 a: 3 μm

Thickness of electroless copper plating layer 6 a: 1 μm

Diameter of through hole 4: 100 μm

Width of interconnection pattern 10: 40 μm

Diameter of ball pad 10 a: 50 μm

Diameter of ball pad 10 b: 100 μm

Chief material of DFR 8: acrylic resin

Constituents of Ni/Au plating solution: Nickel sulfate bath and goldcyanide bath

Cleaning treatment on electroless: buffing, jet scrubbing, and acidcleaning copper plating layer 6 a

Bake treatment of DFR 8: 100° C., 30 min

Release solution of DFR 8: 3% NaOH solution, 50° C.

Etchant of Cu: soft etching solution of pH 7.0 of soda persulfate

On the ball pads and through holes 4, the Ni/Au films 9 shown in FIG. 24were formed.

Peel test of Ni/Au layer 9: by a peel test using a cellophane adhesivetape on the market, a preferable result, no peeling of the Ni/Au layer,could be obtained.

What is claimed is:
 1. A method for manufacturing a chip package,including the steps of: forming a plating resist pattern inverse to aninterconnection pattern on the surface of a metal layer, which comprisesa copper foil, an electroless copper plating layer, and an electrolyticplating layer, formed on one side or both sides of a resin substrate;applying an electric current to the metal layer so as to form Ni and Aufilms by electroplating on the metal layer surface which is not coveredwith the plating resist pattern; and removing the plating resist patternso as to etch the metal layer using the Ni/Au films as an etching mask.2. The method for manufacturing a chip package according to claim 1,wherein the metal layer which comprises an electroless copper platinglayer, or a copper foil and an electroless copper plating layer, and thestep of applying an electric current to the metal layer so as to form acopper film by electroplating on the metal layer surface which is notcovered with the plating resist pattern is put between the step offorming the plating resist pattern inverse to the interconnectionpattern and the step of forming Ni and Au films by electroplating. 3.The method for manufacturing a chip package according to claim 2,wherein a soft etching solution having a principal constituent of sodiumpersulfate or mixture of hydrogen peroxide and sulfuric acid is used asan etchant of the metal layer.
 4. The method for manufacturing a chippackage according to claim 1 or claim 2 including the step of conductingelectroless plating and electroplating treatment of copper on the sidewalls of through holes after forming the through holes in the resinsubstrate.
 5. The method for manufacturing a chip package according toclaim 1 or claim 2, wherein a dry film resist having a principalconstituent of acrylic resin is used for forming the plating resistpattern inverse to the interconnection pattern.
 6. The method formanufacturing a chip package according to claim 5, wherein a cleaningtreatment is conducted on the metal layer surface before forming theplating resist pattern inverse to the interconnection pattern.
 7. Themethod for manufacturing a chip package according to claim 1 or claim 2,wherein a liquid resist having a principal constituent of acrylic resinis used for forming the plating resist pattern inverse to theinterconnection pattern.
 8. The method for manufacturing a chip packageaccording to claim 1 or claim 2, wherein a baking treatment is conductedon the plating resist and/or the plating resist pattern inverse to theinterconnection pattern before forming Ni and Au films.
 9. The methodfor manufacturing a chip package according to claim 1, wherein analkaline solution having a principal constituent of copper amine complexor tetraaminecopper (II) chloride is used as an etchant of the metallayer.